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dc.contributor.authorLozito, Gabriele-Maria
dc.contributor.authorLaudani, Antonio
dc.contributor.authorRiganti-Fulginei, Francesco
dc.contributor.authorSalvini, Alessandro
dc.date.accessioned2016-09-30T09:17:18Z
dc.date.available2016-09-30T09:17:18Z
dc.date.issued2014
dc.identifier.citationAdvances in electrical and electronic engineering. 2014, vol. 12, no. 1, p. 30-39 : ill.cs
dc.identifier.issn1336-1376
dc.identifier.issn1804-3119
dc.identifier.urihttp://hdl.handle.net/10084/112085
dc.description.abstractThis paper documents the research towards the analysis of different solutions to implement a Neural Network architecture on a FPGA design by using floating point accelerators. In particular, two different implementations are investigated: a high level solution to create a neural network on a soft processor design, with different strategies for enhancing the performance of the process; a low level solution, achieved by a cascade of floating point arithmetic elements. Comparisons of the achieved performance in terms of both time consumptions and FPGA resources employed for the architectures are presented.cs
dc.format.extent1162555 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoencs
dc.publisherVysoká škola báňská - Technická univerzita Ostravacs
dc.relation.ispartofseriesAdvances in electrical and electronic engineeringcs
dc.relation.urihttp://dx.doi.org/10.15598/aeee.v12i1.831cs
dc.rights© Vysoká škola báňská - Technická univerzita Ostrava
dc.rightsCreative Commons Attribution 3.0 Unported (CC BY 3.0)
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/
dc.subjectembedded floating pointcs
dc.subjectFPGAcs
dc.subjectneural networkscs
dc.subjectsoft-core processorcs
dc.subjectVHDLcs
dc.titleFPGA implementations of feed forward neural network by using floating point hardware acceleratorscs
dc.typearticlecs
dc.identifier.doi10.15598/aeee.v12i1.831
dc.rights.accessopenAccess
dc.type.versionpublishedVersioncs
dc.type.statusPeer-reviewedcs


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