Early Area and Power Estimation Model for Rapid System Level Design and Design Space Exploration

Abstract

Power and area estimation in the early stage of designing is very critical for a system. This paper presents the neural network-based early area and power estimation model. The flow starts with the training of the neural network model from the selected behav- ioral level parameters, which imposes to provide ac- curate estimations. The model accuracy is validated against ITC99 benchmark programs. The run-times are faster than the synthesis run-times. For the ASIC- based designs, the proposed model took 5 seconds, while Synopsys Design Compiler took 5 minutes. In terms of timing, the estimation speed is more than the order of magnitude faster than the conventional synthesis- based approach. The modeling methodology provides a better, accurate, and fast area and power estima- tions, at an early stage of the Very-Large-Scale Integra- tion (VLSI) design. In addition, the model eliminates the need for synthesis-based exploration and provides the design picking before synthesis.