Hardware Accelerated Neural Networks

Abstract

This thesis shows the possibilities of hardware acceleration for neural network algorithms. First theoretical part introduces the basics of neural network units, weights, the activation function and the training process. Multi-layer perceptron used in pattern recognition is then deeply analyzed from the view of training algorithms. The error back-propagation process is described in details. Second part of the thesis discusses the options in parallelization of the error back-propagation process, where two mplementation approaches, CPU implementation and GPU implementation, are proposed. The practical part then, includes detailed description of chosen GPU implementation utilizing CUDA and shows the results of performance testing on a high end CUDA device. Work also includes brief description of currently available software solutions for neural networks.