Ověření vlivu impedance zátěže na tvar logického signálu - laboratorní úloha

Abstract

The aim of this bachelor's thesis was to create a laboratory task that would familiarize students with the influence of load impedance on the shape of logical signals. The thesis first deals with the selection of appropriate logic standards for demonstrating the influence of load impedance and transmission lines on the quality of the received signal. A Xilinx Nexys 3 development board, equipped with an FPGA Spartan 6 chip, is used as the source of digital signals. The FPGA configuration was created in VHDL language and allows the use of various parameters for output pins, such as signal transition speed, current capacity, and output impedance. Furthermore, a laboratory instrument was created for artificial signal loading, which allows the output signal to be loaded using various combinations of RLC elements and metallic wiring connections. In practical measurement, the student can observe the negative effects of load on the signal, as well as proper impedance matching of the load by means of the mentioned resources. They can also evaluate the quality of the signal using the eye diagram. After completing the laboratory task, the student should be familiar with the basic issues of signal transmission in digital systems.