Simulácia a testovanie kombinačných obvodov vo VHDL

Abstract

The bachelor thesis deals with the simulation and subsequent testing of combinational circuits in VHDL. The theoretical part of the bachelor thesis describes basic logic circuits, their definitions and functions. It discusses the types and definitions of combinational logic circuits. The practical part of the bachelor thesis describes the results of simulations and testing of different types of combinational logic circuits. For simulation and testing, simulation tools for VHDL in Linux are used.