Modul pro automatické testování a vyhodnocování simulací logických obvodů

Abstract

This thesis is being created to support the teaching of logic circuits at the VŠB – Technical University of Ostrava. The goal is to create a system that offers students the possibility to test their knowledge in the compilation of logic diagrams. For teachers the system should offer to facilitate the testing of students discussed the issue of when the teacher put into the system only award and evaluation is carried out automatically and without any further assistance. Application access is through a web interface, through which the applet runs with the editor of schemes, in which the simulation of involvement.