Heuristic synthesis of reversible logic - a comparative study

dc.contributor.authorCheng, Chua Shin
dc.contributor.authorSingh, Ashutosh Kumar
dc.date.accessioned2016-07-11T09:56:43Z
dc.date.available2016-07-11T09:56:43Z
dc.date.issued2014
dc.description.abstractReversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based). All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.cs
dc.format.extent779012 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationAdvances in electrical and electronic engineering. 2014, vol. 12, no. 3, s. 210-225 : ill.cs
dc.identifier.doi10.15598/aeee.v12i3.916
dc.identifier.issn1336-1376
dc.identifier.issn1804-3119
dc.identifier.urihttp://hdl.handle.net/10084/111816
dc.language.isoencs
dc.publisherVysoká škola báňská - Technická univerzita Ostravacs
dc.relation.ispartofseriesAdvances in electrical and electronic engineeringcs
dc.relation.urihttp://dx.doi.org/10.15598/aeee.v12i3.916cs
dc.rights© Vysoká škola báňská - Technická univerzita Ostrava
dc.rightsCreative Commons Attribution 3.0 Unported (CC BY 3.0)
dc.rights.accessopenAccess
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/
dc.subjectancilla inputcs
dc.subjectgarbage outputcs
dc.subjectheuristiccs
dc.subjectquantum costcs
dc.subjectreversible logiccs
dc.subjectsynthesiscs
dc.titleHeuristic synthesis of reversible logic - a comparative studycs
dc.typearticlecs
dc.type.statusPeer-reviewedcs
dc.type.versionpublishedVersioncs

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