Komprese videosignálu s využití pokročilých funkcí mikrokontroléru

Abstract

This thesis explores the possibilities of JPEG compression on the MCXN947 microcontroller. Two systems are designed – one for capturing, compressing, and transmitting image data from a camera via Ethernet using the UDP protocol, and another for receiving, decompressing, and displaying the data on an LCD screen. The work describes the microcontroller’s architecture, the principles of JPEG compression, and the implementation of both systems using an available library for JPEG compression. The library is subsequently optimized using the PowerQuad accelerator and parallel processing on dual cores, and their impact on the efficiency of real-time image data processing is analyzed.

Description

Subject(s)

JPEG, MCX-N947, microcontroller, Ethernet, PowerQuad, Cortex-M33, DMA, parallelization, optimization, compression, decompression, codec, camera, display

Citation