Ultra low power high speed domino logic circuit by using FinFET technology

Abstract

Scaling of the MOSFET face greater challenge by extreme power density due to leakage current in ultra deep sub-micron (UDSM) technology. To overcome from this situation double gate device like FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gate, which mitigate shorter channel effect and exponentially reduces the leakage current. In this research paper utilize the property of FinFET in domino logic, for high speed operation and reduction of power consumption in wide fan-in OR gate. Proposed circuit is simulated in FinFET technology by BISM4 model using HSPICE at 32nm process technology at 250C with CL=1pF at 100MHz frequency. For 8 and 16 input OR gate we save average power 11.5%,11.39% in SFLD, 22.97%, 18.12% in HSD, 30.90%, 34.57% in CKD in SG mode and for LP mode 11.26%, 15.78% in SFLD, 19.74%, 17.94% in HSD, 45.23%, 34.69% in CKD respectively