Použití časových omezení při návrhu programovatelné logiky – laboratorní úloha

Abstract

The aim of this Bachelor Thesis is the creation of laboratory task for the demonstration of timing constraints influences during suggestion of programmable logic in FPGA. Briefly, there is a description of FPGA techniques and creation technology of field programmable gate array thanks to VHDL language in this work. Further meeting available constraints, mainly focused on timing constraints that are included into the laboratory task. The results of this Bachelor Thesis enable practical verification of timing constraints advantages for suggestion of FPGA logic. These benefits contains the increase of working frequency, saving of used logic, and thanks to the control of clock signal parameters we can avoid the creation of uncertainty that can endanger functionality of the whole circuit. The aim of this Bachelor Thesis is to closely describe, especially to students, suggestion and functionality of timing constraints. The work itself can also serve as Czech instructions to further education in the area of constraints generally.