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dc.contributor.authorAbdelrahman, Ahmed Awadalla
dc.contributor.authorFouad, Mohamed Mahmoud
dc.contributor.authorOrješek, Richard
dc.contributor.authorDahshan, Hisham Mohamed
dc.date.accessioned2017-12-01T10:05:06Z
dc.date.available2017-12-01T10:05:06Z
dc.date.issued2017
dc.identifier.citationAdvances in electrical and electronic engineering. 2017, vol. 15, no. 3, p. 526-535 : ill.cs
dc.identifier.issn1336-1376
dc.identifier.issn1804-3119
dc.identifier.urihttp://hdl.handle.net/10084/122131
dc.description.abstractThe Advanced Encryption Standard (AES) is One of the most popular symmetric block cipher because it has better efficiency and security. The AES is computation intensive algorithm especially for massive transactions. The Graphics Processing Unit (GPU) is an amazing platform for accelerating AES. it has good parallel processing power. Traditional approaches for implementing AES using GPU use 16 byte per thread as a default granularity. In this paper, the AES-128 algorithm (ECB mode) is implemented on three different GPU architectures with different values of granularities (32,64 and 128 bytes/thread). Our results show that the throughput factor reaches 277 Gbps, 201 Gbps and 78 Gbps using the NVIDIA GTX 1080 (Pascal), the NVIDIA GTX TITAN X (Maxwell) and the GTX 780 (Kepler) GPU architectures.cs
dc.format.extent495401 bytes
dc.format.mimetypeapplication/pdf
dc.languageNeuvedenocs
dc.language.isoencs
dc.publisherVysoká škola báňská - Technická univerzita Ostravacs
dc.relation.ispartofseriesAdvances in electrical and electronic engineeringcs
dc.relation.urihttp://dx.doi.org/10.15598/aeee.v15i3.2324
dc.rights© Vysoká škola báňská - Technická univerzita Ostrava
dc.rights© Vysoká škola báňská - Technická univerzita Ostrava
dc.rightsAttribution 4.0 International*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.subjectAEScs
dc.subjectcompute unified device architecture (CUDA)cs
dc.subjectGPUcs
dc.subjectgranularitycs
dc.titleAnalysis on the AES implementation with various granularities on different GPU architecturescs
dc.typearticlecs
dc.identifier.doi10.15598/aeee.v15i3.2324
dc.rights.accessopenAccess
dc.type.versionpublishedVersion
dc.type.statusPeer-reviewed


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