Dynamic Power Consumption and Delay Analysis for Ultra-Low Power 2 to 1 Multiplexer Designs

Kumar, Nishant; Mittal, Poornima; Rawat, Bhawna; Mittal, Mudit

dc.contributor.author	Kumar, Nishant
dc.contributor.author	Mittal, Poornima
dc.contributor.author	Rawat, Bhawna
dc.contributor.author	Mittal, Mudit
dc.date.accessioned	2021-07-16T09:55:44Z
dc.date.available	2021-07-16T09:55:44Z
dc.date.issued	2021
dc.identifier.citation	Advances in electrical and electronic engineering. 2021, vol. 19, no. 2, p. 145 - 154 : ill.	cs
dc.identifier.issn	1336-1376
dc.identifier.issn	1804-3119
dc.identifier.uri	http://hdl.handle.net/10084/145067
dc.description.abstract	This paper highlights a comparative analysis of eight diverse techniques for 2 to 1 multiplexer implementation. The functionality is identical but significant differences in dynamic power consumption and propagation delay are observed. This paper aims to enable the designer to pick out the best fit structure for a specific application in keeping with their design requirement. The multiplexers are designed at 90 nm technology node and simulated at a supply voltage of 1V.	cs
dc.language.iso	en	cs
dc.publisher	Vysoká škola báňská - Technická univerzita Ostrava	cs
dc.relation.ispartofseries	Advances in electrical and electronic engineering	cs
dc.relation.uri	https://doi.org/10.15598/aeee.v19i2.3821	cs
dc.rights	© Vysoká škola báňská - Technická univerzita Ostrava
dc.rights	Attribution-NoDerivatives 4.0 International	*
dc.rights.uri	http://creativecommons.org/licenses/by-nd/4.0/	*
dc.subject	average power dissipation	cs
dc.subject	CMOS	cs
dc.subject	dynamic power	cs
dc.subject	leakage power	cs
dc.subject	low power application	cs
dc.subject	power delay product	cs
dc.subject	standard cells	cs
dc.title	Dynamic Power Consumption and Delay Analysis for Ultra-Low Power 2 to 1 Multiplexer Designs	cs
dc.type	article	cs
dc.identifier.doi	10.15598/aeee.v19i2.3821
dc.rights.access	openAccess	cs
dc.type.version	publishedVersion	cs
dc.type.status	Peer-reviewed	cs