dc.contributor.author | Tripathi, Priyans | |
dc.contributor.author | Yadava, Narendra | |
dc.contributor.author | Gupta, Mangal Deep | |
dc.contributor.author | Chauhan, Rajeev Kumar | |
dc.date.accessioned | 2022-04-12T08:56:55Z | |
dc.date.available | 2022-04-12T08:56:55Z | |
dc.date.issued | 2022 | |
dc.identifier.citation | Advances in electrical and electronic engineering. 2022, vol. 20, no. 1, p. 73 - 85 : ill. | cs |
dc.identifier.issn | 1336-1376 | |
dc.identifier.issn | 1804-3119 | |
dc.identifier.uri | http://hdl.handle.net/10084/146033 | |
dc.description.abstract | The choice of gate metal technology for
junctionless transistors needs to have diverse charac-
teristics as metals have distinct work functions and
hence, they show incompatibility while tailoring thresh-
old of the device. In such a scenario, bimetallic stacked
gate can be a promising candidate to present wide
range of tunable work functions required for nano-
regime junctionless transistors. This paper explores the
electronic phenomena occurring at metal-metal inter-
face and the impact of Platinum (Pt)/Titanium (Ti)
bimetallic stacked gate-based work function tunabil-
ity on the RF and thermal performances of p-type
window-based Silicon on Insulator Junctionless Tran-
sistor (SOI JLT) using numerical simulator SILVACO
ATLAS. The parameters considered for performance
evaluation are ON-state current (ION ), OFF-state cur-
rent (IOF F ), ION /IOF F ratio, transconductance (gm),
cutoff frequency (fT ), Transconductance Frequency
Product (TFP), Intrinsic Gate Delay (IGD), intrin-
sic gain (AV ), and Global Device Temperature (GDT).
The gm, fT , TFP, AV and GDT improve for modi-
fied over conventional in the ON state at higher work
function, while IGD improves at lower work function.
The improvements of 11.7 % and 2.21 % are obtained
in maximum gm and fT , respectively, for modified tran-
sistor over conventional. The findings suggest that
bimetallic stacked gate modified SOIJLT is a better op-
tion than conventional for low-power RF application. | cs |
dc.language.iso | en | cs |
dc.publisher | Vysoká škola báňská - Technická univerzita Ostrava | cs |
dc.relation.ispartofseries | Advances in electrical and electronic engineering | cs |
dc.relation.uri | https://doi.org/10.15598/aeee.v20i1.4258 | cs |
dc.rights | © Vysoká škola báňská - Technická univerzita Ostrava | |
dc.rights | Attribution-NoDerivatives 4.0 International | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nd/4.0/ | * |
dc.subject | bimetallic stacked gate | cs |
dc.subject | junctionless transistor (JLT) | cs |
dc.subject | radio frequency (RF) | cs |
dc.subject | Silicon-on- Insulator (SOI) | cs |
dc.subject | thermal performance and tunable work function | cs |
dc.title | Impact of Work Function Tunability on Thermal and RF Performance of P-type Window based Junctionless Transistor | cs |
dc.type | article | cs |
dc.identifier.doi | 10.15598/aeee.v20i1.4258 | |
dc.rights.access | openAccess | cs |
dc.type.version | publishedVersion | cs |
dc.type.status | Peer-reviewed | cs |