Simulování číslicových obvodů v prostředí Proteus

Abstract

This bachelor thesis deals with the simulation of digital circuits in the Proteus environment. Part of the work is a guide for creating simulations together with a closer acquaintance with the previously mentioned environment. There is an overview of digital technology, which aims to approach simulated digital circuits and understand their principle. Sample laboratory tasks for both combinational and sequential logic circuits are described there, together with a practical design of a digital circuit in the form of a digital lock. Another element of the practical part is the measurement of the gate characteristics of the negated logic product. This part is focused on a clear comparison of the simulation model and the real circuit behaviour.