Simulation of electrical parameters for Ru/Ta2O5/SiO2/Si(p) high-k MOS structure

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AEEE-2008-7-1-2-385-Racko.pdf (168.14 KB)

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2008

Authors

Racko, J.
Harmatha, L.
Breza, J.
Benko, P.
Donoval, D.

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Žilinská univerzita v Žiline. Elektrotechnická fakulta
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Abstract

The contribution presents the results of simulation of direct tunnelling of free charge carriers through a thin gate insulator in MOS structures consisting of a Ta2O5/SiO2 bilayer taking into account also indirect tunnelling of free charge carriers through the SiO2/Si interface traps. The calculated I–V and C–V curves reveal the processes of electron and hole tunnelling through the insulator-to-semiconductor potential barrier that can be divided into four classes.

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Advances in electrical and electronic engineering. 2008, vol. 7, no. 1, 2, p. 385-388.

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http://hdl.handle.net/10084/84220

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AEEE. 2008, vol. 7
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