Simulation of electrical parameters for Ru/Ta2O5/SiO2/Si(p) high-k MOS structure
| dc.contributor.author | Racko, J. | |
| dc.contributor.author | Harmatha, L. | |
| dc.contributor.author | Breza, J. | |
| dc.contributor.author | Benko, P. | |
| dc.contributor.author | Donoval, D. | |
| dc.date.accessioned | 2011-02-10T08:07:57Z | |
| dc.date.available | 2011-02-10T08:07:57Z | |
| dc.date.issued | 2008 | |
| dc.description.abstract | The contribution presents the results of simulation of direct tunnelling of free charge carriers through a thin gate insulator in MOS structures consisting of a Ta2O5/SiO2 bilayer taking into account also indirect tunnelling of free charge carriers through the SiO2/Si interface traps. The calculated I–V and C–V curves reveal the processes of electron and hole tunnelling through the insulator-to-semiconductor potential barrier that can be divided into four classes. | en |
| dc.format.extent | 172175 bytes | cs |
| dc.format.mimetype | application/pdf | cs |
| dc.identifier.citation | Advances in electrical and electronic engineering. 2008, vol. 7, no. 1, 2, p. 385-388. | en |
| dc.identifier.issn | 1336-1376 | |
| dc.identifier.uri | http://hdl.handle.net/10084/84220 | |
| dc.language.iso | en | en |
| dc.publisher | Žilinská univerzita v Žiline. Elektrotechnická fakulta | en |
| dc.relation.ispartofseries | Advances in electrical and electronic engineering | en |
| dc.relation.uri | http://advances.utc.sk/index.php/AEEE | en |
| dc.rights | Creative Commons Attribution 3.0 Unported (CC BY 3.0) | |
| dc.rights | © Žilinská univerzita v Žiline. Elektrotechnická fakulta | |
| dc.rights.access | openAccess | |
| dc.rights.uri | http://creativecommons.org/licenses/by/3.0/ | |
| dc.title | Simulation of electrical parameters for Ru/Ta2O5/SiO2/Si(p) high-k MOS structure | en |
| dc.type | article | en |
| dc.type.status | Peer-reviewed | cs |
| dc.type.version | publishedVersion | cs |