Simulácia a testovanie sekvenčných obvodov vo VHDL
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Vysoká škola báňská – Technická univerzita Ostrava
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Abstract
The aim of the bachelor thesis is to simulate and test sequential circuits using VHSIC Hardware Description Language based on theoretical background. The theoretical part of the bachelor thesis deals with the analysis of sequential circuits. The first theoretical chapter describes logic circuits. The second theoretical chapter deals with the theoretical analysis and describes sequential circuits. The practical part of the bachelor thesis deals with the description of simulation results and testing of different types of sequential circuits, based on the theoretical background. Testing and simulation is performed using simulation tools for Linux.
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counters, finite state machines, flip-flop circuits, FPGA, FSM, sequential circuits, registers, simulation, testing, VHDL